IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543

This article has now been updated. Please use the final version.

Floorplanner for multi-core micro-processors in 3D ICs with interlayer cooling system
Wei GuoMinxuan ZhangPeng LiChaoyun Yao
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JOURNAL FREE ACCESS Advance online publication

Article ID: 12.20150489

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Abstract

3D ICs is a solution for multi-core processors, with critical challenge of internal thermal problem. A new solution for this problem is interlayer cooling system, which expands the floorplan design space of micro-processors in 3D ICs. This work proposes a floorplanner for multi-core processor in 3D ICs with interlayer cooling system, integrated with greedy and particle swarm optimization method. The results show that the maximal temperature and temperature gradient reduced by 10.3°C and 9.2°C respectively, compared with the baseline design in 3 active device layers.

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© 2015 by The Institute of Electronics, Information and Communication Engineers
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