Design and Implementation of a Novel LT Codec Architecture on TTA Based Codesign Environment

Abstract

The main aim of this paper is to explain the generation technique of application specific function units (FUs) for reducing the number of instructions in Luby Transform (LT) codec processor. For this reason, Transport Triggered Architecture (TTA) is taken as an active processor template for designing a high-speed TTA-based LT codec processor using TTA-based Co-design Environment (TCE) tool. In this design, processor architectures named as P₁, P₂, P₃ , P₄, P₅, and P₆ are generated to gradually improve the performance of the TTA processor. P₆ took only 4,466 cycles and 43 ms to simulate an LT codec system. In this paper, P₆ of the TCE tool took only a single iteration to generate the decoded signal.