A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler

Abstract

A novel low-power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented. Compared with the conventional topologies, one of the precharge stages in the TSPC flip-flops is eliminated, and the number of switching stages is reduced to 5. The prescaler is implemented in a standard 0.18-μm CMOS process. It achieves the maximum operating frequency of 5.7GHz with a measured power consumption of 0.95 mW and 0.98mW in divide-by-3 mode and divide-by-2 mode, respectively, when operated at 1.5-V power supply.