Universal closed-form expressions for the inductance of tapered through silicon vias (T-TSVs) based on vector magnetic potential

Zheng Mei; Gang Dong; Yintang Yang; Junping Zheng; Yingbo Zhao; Weijun Zhu

doi:10.1587/elex.13.20160621

This article has now been updated. Please use the final version.

Universal closed-form expressions for the inductance of tapered through silicon vias (T-TSVs) based on vector magnetic potential

Zheng Mei, Gang Dong, Yintang Yang, Junping Zheng, Yingbo Zhao, Weijun Zhu

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Keywords: three-dimensional integrated circuits (3D ICs), tapered through silicon vias (T-TSVs), inductance, vector magnetic potential

JOURNAL FREE ACCESS Advance online publication

Article ID: 13.20160621

DOI https://doi.org/10.1587/elex.13.20160621

The final version of this article is now available: Vol. 13 (2016), No. 18 pp. 20160621-20160621

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Abstract

This paper proposes novel formulas for the calculation of the parasitic inductance of Tapered-Through Silicon Vias (T-TSVs), considering the TSVs located in adjacent layers. The formulas can not only be reduced to calculate the self-partial inductance and mutual-partial inductance of T-TSVs located in the same layer but also be used for cylindrical TSVs when the slope angle is 90°. The comparison between the results of the proposed formulas and Ansoft Q3D shows that the proposed formulas have very high accuracy with a maximum error of 2.5%.

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