A Priority-based Selective Bit Dropping Strategy to Reduce DRAM and SRAM Power in Image Processing

Abstract

By adopting the human visual system property, a priority-based selective bit dropping strategy to reduce DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) power consumption is presented in this paper. The tradeoff between power consumption and output quality is explored as well. During the data flow in image processing, the original image data are first processed with our proposed strategy, from which the number of bit-'1' in lower part of each pixel is reduced. Then the approximate data are pushed into the DRAM and SRAM for further computation, where the refresh power consumption for DRAM is reduced due to the less bit-'1' in each data and the write power consumption for SRAM is also reduced due to the lower switch probability in write operation. The proposed strategy has been realized with digital logic circuits and the approximate image data are processed by the Discrete Cosine Transform (DCT) in simulation. The results show that 27.7% refresh power reduction on average for DRAM can be achieved and the SRAM also obtained 21.7% write power reduction with negligible overhead. As for the final output quality of the images, only 1.01dB losses for Peak-Signal-Noise-Ratio (PSNR) is presented (about 3% lower than accurate processing) after the DCT processing.