A Unified System Level Error Model of Crosstalk and Electromigration for On-Chip Interconnect

Abstract

The continuous scaling of feature dimensions and the much more complex IC composition are pushing interconnect reliability to its limit, resulting in many fault tolerant interconnect schemes being proposed. At the system level, real-scenario platform simulation is conducted to choose the optimal combination of each part, and various fault tolerant schemes are also compared. In a real-scenario platform simulation, a more practical error model in addition to white noise is needed. So, this paper suggests integrative simple noise and error probability model using the regression analysis with respect to physical behaviors of crosstalk and electromigration. This model can be used in system level simulation to choose an optimal fault-tolerant scheme. In this paper, the integrated crosstalk glitch, and delay model had over 99% accuracy with referenced model, and can apply to system level simulation. 65 nm, 32 nm, 22 nm technologies were used to extract the interconnect parasitic.