Efficient AES Cipher on Coarse-Grained Reconfigurable Architecture
Keywords:
Coarse-Grained Reconfigurable Architecture(CGRA),
Advanced Encryption Standard(AES),
Mapping Scheme
Article ID: 14.20170449
Details
Article ID: 14.20170449
By exploring the mapping schemes with dataflow graph(DFG) transformation and different granularity of task-level parallelism, we presented various AES implementations on a coarse grained reconfigurable architecture(CGRA) to meet the requirements raging from high performance to low power. In comparison with published AES cipher implementations on programable processors, our AES cipher has 14.7∼121.4× higher energy efficiency. Moreover, the design shows the advantage over other CGRAs with 1.3∼4.5× energy efficiency improvement.
