Standby power reduction using dynamic standby control with voltage keeper

抄録

This paper presents dynamic standby control (DSC) with voltage keeper for further standby power reduction. As compared to the reported DSC, the new modified DSC can be kept deeply cut-off with negative overdrive voltage as well. Besides, a bootstrapped voltage keeper directly recharges the boosted node of power gate, which prevents leakage current during the recharging period. However, total standby power includes power overhead from DSC. Tuning the recharging rate of the proposed DSC appropriately achieves energy-efficient standby power. As a result, our proposal shows that minimized standby current can be found by an appropriate recharging rate even in different PVT conditions. The design is implemented in 180nm CMOS process. Measured results show that standby power is suppressed at 0.8V. Minimum standby power of only 16nW is achieve where the recharging rate is 10kHz.