J-STAGE Home  >  Publications - Top  > Bibliographic Information

IEICE Electronics Express
Article ID: 14.20170820



A dynamic log-likelihood ratio (DLLR) scheme based on expectation-maximization (EM) algorithm for the decoding of low-density parity-check (LDPC) codes in NAND flash memory is proposed. When LDPC soft decoding fails, the DLLR scheme employs the EM algorithm to estimate the parameters of the threshold voltage distribution of NAND flash memory, and then recalculates the LLR values for decoding. Simulation results show that the proposed scheme can significantly improve the error correcting performance of LDPC soft decoding in NAND flash memory.

Copyright © 2017 by The Institute of Electronics, Information and Communication Engineers

Article Tools

Share this Article