1) College of Electronic and Information Engineering Nanjing University of Aeronautics and Astronautics
2) College of Electrical Engineering, Anhui Polytechnic University
MISTY1, RAM, FPGA, LUTs
The final version of this article with its full bibliographical information is available. To access the article, click here (Vol. 14 (2017), No. 18 pp. 20170841-20170841).
This letter proposes highly efficient MISTY1 8-rounds pipe-lined architecture for wireless networks. A novel methodology is adopted for implementation of MISTY1 substitution functions by optimizing S9 and S7 LUTs (Look-Up Tables) to minimize the silicon area. Besides, a key module FI function is compliant to double edge-trigger the optimized S9 LUTs. This leads to substantial reduction in the pipeline requirements for the proposed hardware architecture. For path delay reduction, logic modifications are made in FI and FO functions realizing efficient and high-speed MISTY1 implementation. FPGA implementation on Xilinx FPGA, Virtex 7 xc7vx690t yielded a throughput value of 16.3 Gbps covering area of 1265 CLB slices.
Edited and published by : The Institute of Electronics, Information and Communication Engineers Produced and listed by : Komiyama Printing Co., LTD.