A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement

Abstract

This paper presents a design-for-test structure of charge-pump phase-locked loops for on-chip jitter measurement, in which use a voltage controlled oscillator based time-to-digital converter. The structure has four key features. 1) By employing a new PFD structure to detect the time difference, it is more suitable for detecting a wide range of timing jitter. 2) The proposed DFT circuit does not need an additional jitter-free reference signal for test using the self-refereed circuit. 3) By using a new TDC structure for on-chip jitter measurement of CP-PLL, it achieves a small test area overhead.4) The proposed DFT structure only has a minor modification on the digital part of the CP-PLL, thus it has a little adverse influence on the circuit performance. The experiment result demonstrates its possibility of detecting a timing jitter of 0.78ps with a measurement error of 5.78%.