IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543

This article has now been updated. Please use the final version.

An Implementation of Low Latency Address-Mapping Logic for SSD Controllers
Yuchan SongHyunjoo SoYongjae ChunHyun-Seok KimYoupyo Hong
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Keywords: SSD, FTL
JOURNAL FREE ACCESS Advance online publication

Article ID: 16.20190521

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Abstract

Solid-state drives (SSDs) are replacing hard-disk drives (HDDs) because of their advantages of light weight, low power, and high speed. A flash translation layer (FTL) is a key to achieving a high efficiency in accessing an SSD. This letter presents an architecture to implement the mapping between the logical address and the physical address as hardwired to reduce the workload of the FTL inside an SSD.

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© 2019 by The Institute of Electronics, Information and Communication Engineers
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