A 0.6V high-swing gate-switching charge pump for PLL with current self-matching technique in 28nm CMOS

Abstract

This letter presents a low voltage high-output-swing gate-switching charge pump (CP) used in phase-locked loops (PLL). The current self-matching technique is proposed to dynamically bias the gate of the current source transistors corresponding to output voltage fluctuation, keeping charging and discharging currents constant. To overcome the voltage margin issues under low supply voltage, a master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is proposed as the error amplifier of the negative feedback loop. The current mismatch of less than 2% is realized in the voltage range from 0.05V to 0.55V. A prototype of the proposed CP is designed and fabricated in TSMC 28nm CMOS process under a 0.6V supply voltage. Charging and discharging currents are designed to be identical during the entire reset impulse. The measured reference spur is less than -59.4 dBc.