Analysis and Evaluation of Noise Coupling Between Through-Silicon-Vias

Abstract

Three-dimensional stacking of ICs with through-silicon-vias (TSVs) is one of the most expected way to integrate an enormous scale system in a small footprint. Shortened distance and expanded interconnect area are proofed to enable low-power, ultra-wide bandwidth communication among logic, memory, and analog component. In the 3-D integrated system with massive vertical interconnects, noise coupling among TSVs can be problem, by degrading signal integrity. We made a simple model to estimate noise coupling among TSVs and analyzed the coupling strength against parasitic capacitance of liner oxide. A test chip is fabricated, and the noise coupling strength is evaluated through on-chip waveform capturing circuitry. The analytical result and measured result show good consistency, and they indicate smaller size TSVs show better noise isolation characteristics as well as process simplicity.