Analysis and optimization for hardware implementation of Sine/Cosine with faithful rounding and monotonicity through piecewise quadratic polynomial

Abstract

Piecewise quadratic polynomial approximation is a well-established hardware function evaluation technique. In this paper, we demonstrate the analysis and optimization of hardware implementation of sine and cosine through piecewise quadratic polynomial for single-precision floating-point operations. First, detailed approximation error analysis was used to rapidly obtain the non-uniform segmentation and guarantee faithful rounding. Second, theoretical analysis demonstrates that the monotonicity of the algorithm using segmentation is consistent with the original sine and cosine function. Moreover, the bit-width is optimized for the sine and cosine floating-point arithmetic units based on static analysis and dynamic monitoring to reduce the hardware cost. Experimental results show that the implementation for sine and cosine functions meets the requirements of faithful rounding and monotonicity with reasonable hardware cost.