Low Delay AES S-Box Designs Based on Matrix Merging Method

Abstract

In this paper, a low delay circuit structure is proposed for composite field S-box circuit. In the low delay structure, the multiplications over GF((2²)²) are constructed by XOR-AND-XOR-networks, and the multiplicative inverse over GF((2²)²) are constructed by AND-XOR-networks. As XOR-networks are linear operations, they can be further expressed as constant matrix multiplications. In this paper, the adjacent matrix multiplications in S-box are merged to reduce the delay. Compared with previous works, our S-box implementations have lower delay.