FBEL: Enhanced LLR Optimization Algorithm based on the VSER Prediction by Flag Bits in the Bit-flipping Scheme

Bo Zhang; Qi Wang; Xiaolei Yu; Qianhui Li; Jing He; Xianliang Wang; Qianqi Zhao; Xuhong Qiang; Zongliang Huo; Tianchun Ye

doi:10.1587/elex.20.20230113

This article has now been updated. Please use the final version.

FBEL: Enhanced LLR Optimization Algorithm based on the VSER Prediction by Flag Bits in the Bit-flipping Scheme

Bo Zhang, Qi Wang, Xiaolei Yu, Qianhui Li, Jing He, Xianliang Wang, Qianqi Zhao, Xuhong Qiang, Zongliang Huo, Tianchun Ye

Author information

Bo Zhang
Institute of Microelectronics of the Chinese Academy of Sciences
The University of Chinese Academy of Sciences
Qi Wang
Institute of Microelectronics of the Chinese Academy of Sciences
The University of Chinese Academy of Sciences
Xiaolei Yu
Institute of Microelectronics of the Chinese Academy of Sciences
The University of Chinese Academy of Sciences
Qianhui Li
Institute of Microelectronics of the Chinese Academy of Sciences
The University of Chinese Academy of Sciences
Jing He
Institute of Microelectronics of the Chinese Academy of Sciences
The University of Chinese Academy of Sciences
Xianliang Wang
Institute of Microelectronics of the Chinese Academy of Sciences
The University of Chinese Academy of Sciences
Qianqi Zhao
Institute of Microelectronics of the Chinese Academy of Sciences
The University of Chinese Academy of Sciences
Xuhong Qiang
Institute of Microelectronics of the Chinese Academy of Sciences
The University of Chinese Academy of Sciences
Zongliang Huo
Institute of Microelectronics of the Chinese Academy of Sciences
The University of Chinese Academy of Sciences
Tianchun Ye
Institute of Microelectronics of the Chinese Academy of Sciences
The University of Chinese Academy of Sciences

Keywords: NAND Flash, Reliability, LDPC, LLR, Bit-Flipping

JOURNAL FREE ACCESS Advance online publication

Article ID: 20.20230113

DOI https://doi.org/10.1587/elex.20.20230113

The final version of this article is now available: Vol. 20 (2023), No. 11 pp. 20230113-20230113

Details

Abstract

With the development of storage technology, NAND Flash’s reliability becomes more serious. The bit-flipping schemes and low-density parity-check (LDPC) codes are two effective methods to solve this problem. Motivated by error characteristics of NAND Flash and flag bits added by the bit-flipping scheme, an enhanced LLR optimization algorithm of LDPC is proposed based on the prediction of the threshold voltage state error rate (VSER) by flag bits. Compared with the conventional scheme, the proposed algorithm extends the data retention time to 25.44 times. The decoding iterations of LDPC are reduced by up to 87.74%.

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