半導体デバイスの誤点弧メカニズムに関する解析

抄録

This paper analyzes the gate noise performance using simulation and experimental test focused on parasitic inductances of power semiconductor devices' terminals. The gate noise which is over the threshold voltage makes non-active FETs turn on and leads the FETs to a breakdown. Next generation devices which have very high speed switching characteristic are difficult to be dealt with due to the false turn-on problem. The false turn-on mechanism in conventional theory is related to parasitic capacitors and a gate resistor and false turn-on occurs by the current flowing through a reverse transfer capacitor. However, the novel mechanism we proposed is mainly linked to parasitic inductors and recovery current and a non-active FET is switched on due to the oscillation which the energy charged by the current flowing from the source to the gate makes. We verified our theory by experiments, simulations and simplistic circuit equations.