A Hardware Implementation of Back Propagation for Block-based Pulsed Neural Networks

Abstract

Evolvable Hardware (EHW) is reconfigurable hardware which can adopt to unknown new environments. EHW can be implemented combining learning networks such as Neural Networks (NNs) and programmable devices such as FPGA (Field Programmable Gate Array). As such research of EHW, Block-Based Neural Networks (BBNNs) have been proposed. BBNNs have simplified network structures and have been attracting attention with their ease of hardware implementation. In particular, Block-Based Pulsed Neural Networks (BBPNNs) which adopt a pulsed neuron model instead of an analogue neuron model in BBNNs have been proposed in order to solve the problem that BBNNs use many multiplier circuits and require large scale hardware resources for implementation. In addition, applying Back Propagation (BP) which is common learning algorithm of NNs to BBPNNs has been proposed. In this paper, we propose two approximation methods in order to reduce hardware resources which are necessary to apply BP to BBPNNs. In the proposed methods, we approximate input values and derivative values of activation function in BP. Results of computational experiments indicate the validity of the proposed methods.