縦型トランジスタ構造を用いた階層積層型Fe-FET NAND/NANDアレイの提案とそのロジックLSIへの適用検討

抄録

The reduction of fabrication cost without reduction of transistor size is main target for future logic LSI. Previously stacked type Fe-FET NAND/NAND array with the single circuit block architecture for logic circuit had been proposed for this target. In this paper vertical hierarchical stacked type Fe-FET NAND/NAND array and its application to logic LSI have been newly proposed. The feature of the proposed scheme is multiple stacked circuit blocks architecture which operates independently. Compared with the single circuit block architecture the fabrication cost per circuit can be reduced to 36% using 16 stages circuit blocks without sacrificing high speed and low power characteristics. The proposed scheme is one of the most promising candidates for realizing low cost high speed future logic LSI.