Register-Transfer-level CPU Simulator for Computer Architecture Education and Its Quantitative Evaluation

Abstract

This paper reports an educational tool and its evaluation in order for learners to study Computer Architecture, especially in the higher education of Science and Technology field. This tool, which is called Visual CPU Simulator, can provide graphical simulation of assembly program code (instead of machine language) and demonstration of Register-transfer-level micro-operations inside of CPU, namely precise detail of structure and behavior of inner CPU. This educational tool for CPU simulation has been designed and implemented in Javascript language as Web service. Its users select simulation modes by micro step, by machine cycle and by automatic repetition of such cycles. So they can learn how a computer works graphically, recognize inner structure of CPU easily and understand micro-operation based behavior of CPU effectively. This Simulator has been also evaluated through some kinds of questionnaires by learners in many classroom lectures. It is significantly confirmed that the simulator has been very useful and effective to learn Computer Architecture and organization/performance of CPU through its simulating facilities.