<Electrical and Electronic Circuit, LSI>
A Design and Evaluation of 0.5V Filter-less Digital Phase Locked Loop With A New Clock Synchronization Algorithm
2019 Volume 139 Issue 1 Pages 70-75
Details
2019 Volume 139 Issue 1 Pages 70-75
In this paper, we design and evaluate the 0.5V subthreshold filter-less digital PLL. Under the subthreshold region, it's very difficult for analog type PLL using LPF to operate at 0.5V power supply due to narrow signal voltage range. Thus, we design the filter-less digital PLL circuit using our proposed synchronization algorism. As a result, we succeed synchronization without LPF. Power consumption is 373nW at 1048kHz synchronous operation.
The transactions of the Institute of Electrical Engineers of Japan.C
The Journal of the Institute of Electrical Engineers of Japan
