Optimization of High Reliability and Wide SOA 100 V N-LDMOS Transistor

Abstract

This paper describes optimization of a proposed high reliability and wide SOA 100 V N-LDMOS transistor for automotive applications. The drift region of the device is enclosed with two P-type buried layers, dual RESURF structure, and the field plate forming a two-step structure is grounded. The drift region and the field plate were optimized to obtain high hot carrier endurance, high suppression of drain current expansion CE, high breakdown voltage BV_DS, and low specific on-resistance R_ON,SP taking mass production into account. Within the mass production tolerance, the electric field near the gate-side drift region edge of the proposed device is about 70% of that of a conventional device under a high hot carrier generation condition, the drain voltage causing CE of the proposed device is about 20 V higher than that of the conventional device under a high CE generation condition, and the BV_DS - R_ON,SP characteristic of the proposed device is at a state-of-the-art level: BV_DS = 131 V and R_ON,SP = 150 mΩmm² at the worst case. Furthermore, due to slight changing the tolerance range, high ESD endurance of the proposed device could be obtained at the expense of R_ON,SP and suppression of CE a little bit.