IEEJ Transactions on Electronics, Information and Systems
Online ISSN : 1348-8155
Print ISSN : 0385-4221
ISSN-L : 0385-4221
Construction of Ternary Picture Processing Circuits
Noriaki MuranakaShigeru Imanishi
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1995 Volume 115 Issue 3 Pages 337-344

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Abstract

Because the gray and colored images have multiple levels, a multiple-valued logic system for picture processing is more effective as compared with a binary logic system.
This paper proposes several operations and presents ternary digital picture processing circuits (TDPPC's). The TDPPC's consist of ternay/binary level converters, binary/ternary level converters, ternary comparators, neighborhood operation circuits, ternary half adders and center pixel output circuits.
Algorithms for noise reduction, border line extraction, logic difference, thinning, and connected component extraction are used in the developments and designs of the TDPPC's.
Moreover, this paper describes a basic system including a host personal computer. TDPPC's utilized in this system are verified by the algorithms.

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© The Institute of Electrical Engineers of Japan
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