電気学会論文誌C(電子・情報・システム部門誌)
Online ISSN : 1348-8155
Print ISSN : 0385-4221
ISSN-L : 0385-4221
低電圧対応BiCMOSの高速化と寿命予測
山内 経則岡島 義憲黒崎 一秀
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1996 年 116 巻 12 号 p. 1356-1363

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As supply voltage is reduced, a speed superiority of BiCMOS to CMOS can be diminished but BiCMOS even has such an advantage as inducing relatively smaller characteristics degradation on nMOS transistor by supressing the drain voltage in the gate. Introducing a new quantitative methodology to evaluate hot-electron induced characteristics degradation of nMOS transistor, this report expects that both BiNMOS gate and CBiCMOS gate will have a considerable domination to CMOS gate within the voltage rangs from 2.5 volts to 3.3 volts even in the same nMOS transistor characteristics. BiNMOS has 30% faster speed than CMOS only by the effect of amplification of pMOS drain current by a npn transistor. CBiCMOS has 40% faster speed and seven oders of magnitude longer life time than CMOS. The speed improvement comes from amplification of both pMOS and nMOS drain current by npn and pnp transistor, respectivery, and the life time improvement is due to voltage drop effect through pnp transistors on the drain terminal of nMOS transistor. The analytical methodology was also utilized to choose an optimum drain structure. though CMOS necessitate LDD (Lightly Doped Drain), SD (Single Drain) structure, so that the speed of the gates can be further improved and the speed of CBiCMOS is expected to be 45% faster than the CMOS gate. Even in the case of SD structure, the life time of CBiCMOS was estimated to be two orders of magnitude longer than that of CMOS with LDD structure.

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