Design and VLSI Evaluation of High-Speed Cellular Array Divider with Selection Function

Abstract

In recent years, a very high-speed divider is required in real-time applications of digital signal processing and robot control and so on. In this paper, a high-speed cellular array divider with selection function is proposed, which is based on the non-restoring algorithm and can deal with both fixed-point and negative operands in two's complement form. This divider uses new techniques which can generate in parallel both a quotient bit of one row and a partial remainder and CLA bit of its next row. Moreover the delay time of the proposed divider is calculated in terms of a delay of one unit such as NAND gate. Finally, by using PARTHENON, a CAD (Computer Aided Design) system for VLSI, this divider is designed and evaluated. As a result, elimination of delay time for even rows becomes possible. Thus, the delay time can decrease by approximately one-half of the high-speed divider proposed by Cappa and Hamacher which uses the most general high-speed techniques of carry-save and CLA.