障害物の階層的表現に基づく高安全自動車用衝突チェックVLSIプロセッサの設計

抄録

To avoid a traffic accident, it is desired to detect possible collisions between a vehicle and obstacles at high speed. However, high resolution of an obstacle representation results in increase of collision detection time. In this paper, we propose a collision detection VLSI processor based on a hierarchical algorithm. Unless any possible collision is detected in a coarser representation of obstacles, there is no need to detect possible collisions in a finer representation. The VLSI processor consists of several content-addressable memories (CAMs) for parallel matching operation and processing elements (PEs) for parallel coordinate transforma-tion. When the utilized ratios of a CAM and PEs are 100%, minimization of collision detection time under an area constraint can be attributed to the area-time product minimization of a CAM and a PE. As a result, the highest performance is achieved by using a ROM-type CAM and a bit-serial pipelined PE.