Fast Logical Location of Faults in Large Analog Electronic Circuits

抄録

This paper presents a method for fast off-line logical location of faults in analog electronic circuits at the sub-network level and verifies its practical diagnosability. The proposed approach breaks through the previous limitation that all torn terminals (incident nodes) must be accessible and that the mutual-testing method must be utilized to locate the faulty sub-networks. As far as the diagnosability is concerned, its application is more extensive than the unified decomposition approach. Therefore it better satisfies the engineering needs.