An FPGA-implementable chaos circuit with array structure

抄録

In this paper, an FPGA (Field Programmable Gate Array)-implementable chaos circuit with array structure is proposed. The array structure which consists of 1-dimensional chaos circuits enables us to construct an S-dimensional chaos circuit (S=1, 2, 3, ...). Furthermore, the circuit possess exact reproducibility of output signals. The validity of circuit algorithm is confirmed by numerical simulations. The proposed circuit is designed by Verilog-HDL (Hardware Description Language). The experiment concerning the HDL designed circuit shows that the proposed circuit can be implemented into the form of an FPGA.