ICの耐量測定と回路解析を連携したESDに対するプリント配線板の耐量予測手法の開発

抄録

The author proposed an immunity prediction technique to electrostatic discharge (ESD) in the early design stage. The immunity prediction technique was applied to the immunity prediction of ICs on printed wiring boards (PWBs). It consists of a conducted immunity measurement of ICs and a circuit simulation. In the conducted immunity measurement, conducted noise from an ESD-gun is directly injected between a power terminal and a ground terminal of ICs and increased up to a malfunction of the IC. The input voltage at the IC terminals is measured when the IC malfunctions. In the circuit simulation, equivalent circuits are created by modeling the structure of the ESD-gun and the PWBs. The equivalent circuits were analyzed by the circuit simulation and calculated induced voltages between a power layer and a ground layer of the PWBs. Finally, threshold failure levels of the ICs on the printed wiring boards to ESD were defined as ratio of the input voltage measured by the conducted immunity measurement and the induced voltage calculated by the circuit simulation. The results of the immunity prediction technique were verified experimentally.