Low-Inductance Mounting Technique for Inverter with Large Semiconductor Packages

Abstract

This paper proposes a low-inductance mounting technique for an inverter with large semiconductor packages. The following two measures are adopted to decrease the circuit inductance. One is the use of the low-inductance ground pattern of a printed wiring board. The ground pattern is connected in parallel to the main bus bar with lower resistance and higher inductance. The surge current with high di/dt flows selectively in the lower-inductance ground pattern, and the continuous normal current flows in the lower-resistance main bus bar. The other measure is the utilization of an eddy current induced in the heat sink. The eddy current, decreasing circuit inductance, increases in inverse proportion to the distance between the heat sink and a conductor connecting two semiconductor packages. Because of these measures, the circuit inductance decreases to 38% of that of a conventional circuit.