High Speed Image Processor Based on Building-Block Typed Pipeline Architecture

Abstract

This paper presents a high speed image processor for automated visual inspection systems (AVISs), which can continuously process images (512×512×8 bits per frame) through TV cameras at the NTSC video-rato (30 frames per second). The processor has been developed aiming at the solution of a trade-off requisition problem between high speed processing capability and system construction flexibility to cope with various AVIS requirement specifications. The processor bases on a “buildingblock” typed pipeline architecture which enables image processing hardware modules to combine each other in the form of cascade, parallel, and circular connection. This paper discusses a synchronization control method that supports the architecture, which transmits not only image data but also the attributive control signals (sync signal and image identification number, etc.) into image bus, like a data flow machine. This paper describes the processor's system configuration and image processing functions, and also gives some examples of AVIS using the processor. The effectiveness of the processor can be proved by the fact that the number of kinds of AVISs which have been realized by the processor exceeds more than forty.