High-Speed and Transparent Fault-Tolerance by Intra-Board Fault-Masking

Abstract

Computers came to play very important roles in our society such as banking, traffic control, and power distribution control applications. Requirement for high-reliable and 24-hour-a-day continuous computation for various application field is soaring in accordance to globalization of economics and human activity. Fault-tolerant computer systems are required high performance, transparency of fault-tolerance and fault-tolerance of fault-tolerance mechanism itself. This paper presents newly developed fault-tolerance technique, TPR (Triple Processor Check Redundancy) method which is suitable for high-performance computing and has transparency of fault-tolerance. Furthermore, the TPR system has fault-tolerance of fault-tolerance mechanism itself by self-checking MPU (Microprocessing Unit) comparators and independent re-configuration control logics for each redundant system.