1997 Volume 10 Issue 4 Pages 191-203
Force-Directed Scheduling, which is one of effective scheduling methods in high-level synthesis of VLSI design automation, takes the long computational time, though it can optimize hardware cost. Therefore it can not be applied to large scale hardware descriptions. This paper describes an efficient approach for Force-Directed Scheduling. The proposed approach reduces the time for estimating hardware cost by neglecting hardly probable assignments instead of considering all possible assignments as was done in the previous approach. The proposed approach, consequently, can optimize hardware cost for large scale circuits with much less running time.