ITE Technical Report
Online ISSN : 2424-1970
Print ISSN : 1342-6893
ISSN-L : 1342-6893
24.81
Session ID : BCS2000-169/BFO2000-
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Design of the Transmission Line Simulator having a Certain Bit Error Rate
Khingthong InthavongkhamKhamla ChanthavongPhonekeo ChanthamalySomkot MangnomekSusumu IkedaKimio Tanaka
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Abstract

This paper proposes the theoretical design method of transmission line simulator using a combination of the shift register and binary counter circuits. Changing the length of shift register, average bit error rate is controlled. The fundamental concept and its characteristics are described.

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© 2000 The Institute of Image Information and Television Engineers
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