Design of the Transmission Line Simulator having a Certain Bit Error Rate

Khingthong Inthavongkham; Khamla Chanthavong; Phonekeo Chanthamaly; Somkot Mangnomek; Susumu Ikeda; Kimio Tanaka

doi:10.11485/itetr.24.81.0_241

24.81

Session ID : BCS2000-169/BFO2000-

DOI https://doi.org/10.11485/itetr.24.81.0_241

Conference information

Design of the Transmission Line Simulator having a Certain Bit Error Rate

Khingthong Inthavongkham, Khamla Chanthavong, Phonekeo Chanthamaly, Somkot Mangnomek, Susumu Ikeda, Kimio Tanaka

Author information

Keywords: transmission line simulator, maximum length sequence, bit error rate, shift register

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Abstract

This paper proposes the theoretical design method of transmission line simulator using a combination of the shift register and binary counter circuits. Changing the length of shift register, average bit error rate is controlled. The fundamental concept and its characteristics are described.

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