Abstract
Recent advances in downsizing inverters have made it necessary to reduce the surge voltage which can cause trouble in a high-speed power semiconductor that generates a square-wave electric current. Reduction of the wiring inductance between the capacitor and the power module was necessary to reduce the surge voltage. We developed a low-inductance layout technique where an eddy current flows through the cooling plate efficiently using a loop layout for the wiring of the power module. The magnetic flux of the eddy current reduces the wiring inductance by countering the magnetic flux of the wiring. We confirmed that approximately 0.11 times at 1 MHz of the square-wave electric current could reduce the wiring inductance of the trial manufacture power module.
