Transactions of The Japan Institute of Electronics Packaging
Online ISSN : 1884-8028
Print ISSN : 1883-3365
ISSN-L : 1883-3365
Technical Papers
Electrical Characteristics of Build-up Substrates with New Via Structures
Tomoyuki AkahoshiDaisuke MizutaniMotoaki TaniKenichirou AbeShunji BabaMasateru Koide
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2014 Volume 7 Issue 1 Pages 14-19

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Abstract

We investigated the electrical characteristics of the power supply path, which are influenced by the via structures in the build-up substrate. The build-up substrates are composed of core layers and build-up layers, connected by the plated through hole (PTH), and the build-up via (BU via), respectively. This paper investigates how the BU via structures affect the power supply path, and discusses the design constraints of the via structures in the build-up layers.
Three design constraints were considered for the build-up substrate, which comprises six build-up layers laminated on both sides of the core layers. The first constraint limits the BU via stack number, the second is the propriety of the BU via stack on the PTH, and the last limits the number of BU vias connected on the PTH. By changing these design constraints, the power supply paths were designed and compared by simulation and measurement. As a result, the proposed via structures had a significantly difference in terms of resistance and inductance of the power supply path. We have found a via structure that improves the electrical characteristics while also yielding good connectivity and productivity.

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© 2014 The Japan Institute of Electronics Packaging
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