年次大会講演論文集
Online ISSN : 2433-1325
セッションID: 1101
会議情報
1101 三次元実装構造内シリコンチップの残留応力分布(J08-2 電子情報機器,電子デバイスの強度・信頼性評価と熱制御(2) 半導体・界面接合,ジョイントセッション,21世紀地球環境革命の機械工学:人・マイクロナノ・エネルギー・環境)
佐々木 拓也上田 啓貴三浦 英生
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会議録・要旨集 フリー

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抄録
In flip-chip structures, the difference in material properties such as Young's modulus and the coefficient of thermal expansion among a metallic bump, underfill, a silicon chip and a substrate causes the local distribution of residual stress on the chip surface. This stress distribution may cause serious degradation of electronic devices. In this study, we have developed piezoresistive strain sensor chips that consist of single-crystalline silicon for the measurement of residual stress in 3-D stacked structures. The local distribution of residual stress in a two-chip stacked structure was measured by the sensor chips. As a result, the amplitude of the distribution of the residual stress in an upper chip was almost constant of about 200 MPa regardless of the bottom bump alignment. When the two chips were stacked by same bump alignment, the amplitude in the bottom chip decreased to about one third.
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© 2008 一般社団法人日本機械学会
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