The Proceedings of The Manufacturing & Machine Tool Conference
Online ISSN : 2424-3094
2001.3
Session ID : 221
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221 Design Conditions of ET (Engineered Tool) Chip
Kenichiro ImaiHiroshi Hashimoto
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CONFERENCE PROCEEDINGS FREE ACCESS

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Abstract
ET (Engineered Tool) Chip has many small posts on a single crystal diamond surface. And, the post size, form, and distribution pattern can be designed flexibly. This report introduces the design conditions of ET Chip. The depth of cut for the single post [t] was calculated by the locus of post motion equations. And, it was shown that the [tmax] is concerned with | P(s+w) -λ|. (P (s+w) ; post spacing + post width, λ ; [cutting speed v] / [ultrasonic frequency f]) Furthermore, as the | P(s+w) -λ| value increases, the continuous cutting processes changes into the intermittent one. As a results, it was shown that the distribution pattern of post can be designed under P (s+w) -λ ≠0, λ<P (s+w)<2λ, λ>P (s+w)>λ/2 conditions.
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© 2001 The Japan Society of Mechanical Engineers
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