On the Control of Computing-in-memory Devices with Resource-efficient Digital Circuits towards their On-chip Learning

Abstract

Computing-in-memory (CIM) devices have attracted attention because of their high operation efficiency in edge AI, which requires low power operation. This paper proposed a digital circuit architecture controlling the inference and learning of CIM devices such as the RAND chip, which utilizes the non-linearity of ReRAM as memory elements. The RAND chip is used as the CIM device for inference and as external memory for training. The system performance in the XOR identification test achieves the same convergence as the software implementation of the learning core. The proposed learning core achieved efficiency of 7.77 GOPS/W, thereby verifying the effectiveness of the proposed architecture for on-line CIM device learning.