Testing Core-Based System-on-a-Chip Designs

Xiaoqing Wen; Kewal K. Saluja; Kozo Kinoshita

doi:10.11348/reajshinrai.23.4_371

Xiaoqing Wen, Kewal K. Saluja, Kozo Kinoshita

著者情報

キーワード: SoC, core-based design, IP core, testing, fault coverage, stuck-at fault, functional test, ATPG, scan design, BIST, testability, DFT, boundary-scan, design flow, RTL

ジャーナルフリー

2001 年 23 巻 4 号 p. 371-383

DOI https://doi.org/10.11348/reajshinrai.23.4_371

詳細

抄録

This paper reviews a general strategy for testing core-based system-on-a-chip designs. The strategy includes isolating cores from each other to reduce total test complexity, using the best method for testing each individual core, and starting test development for a core early in its design flow. This paper can help design engineers better understand test issues in order to make SoC development successful.

責任著者(Corresponding author)

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