Innovative Avionics Miniaturization by Chip-level Integration Using Vertical Assembly Technique

抄録

In space exploration missions whose resources are severely restricted, miniaturization of onboard avionics by functional integration is crucial. While it seems reasonable to employ the board-level integration in the current technology level of the space community, the ultimate goal is considered to be the chip-level integration. In this paper, an innovative method for vertical assembly of various bare chips is proposed. Silicon substrates, on which bare chips are implemented, are piled up by room-temperature bonding. The room-temperature bonding is based on MEMS (Micro Electro Mechanical Systems) technology. Compared to the vertical assembly preparing the wafer-level TSV (Through Silicon Via), the method is appropriate for space-use of low-volume production because it is not necessary to develop the dedicated chips. Existing bare chips can be vertically integrated into the chip-level integrated avionics. Results of validation tests for the vertically assembled modules such as functional, vibration, and thermal tests, are also shown.