Equivalent Circuit Model for Simulating ESD Discharge Current in ESD Damage Test

抄録

Electrostatic discharge (ESD) damage evaluation methods for common mode choke (CMC) and ESD suppression devices are standardized in IEC 62228-5 Annex E and Annex F, respectively. The significant challenge associated with these tests is the difficulty in measuring the current waveform flowing through the input section of a device under test (DUT) and predicting the current in advance. In this study, we investigated an equivalent circuit model that enables prediction of the discharge current waveform flowing through the DUT in advance using SPICE without measurements. Specifically, we developed an equivalent circuit model consisting of a test board and an ESD gun for LTspice, and subsequently confirmed the validity of the model by comparing the measured output voltage waveforms of the test board with simulated ones. As a result, the simulation circuit model predicts the discharge current through the DUTs and their connected circuit within about 10-30% difference in the first peak voltage and rise time. While there is room for improvement in simulation accuracy from various perspectives, such as the test board and the ESD gun model, this suggests that the simulation circuit model is effective and that the approximate current waveform flowing through the CMC and ESD suppression devices can be predicted by circuit simulation without measurement.