IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology
A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process
Haruki MARUOKAMasashi HIFUMIJun FURUTAKazutoshi KOBAYASHI
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2018 Volume E101.C Issue 4 Pages 273-280

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Abstract

We propose a radiation-hardened Flip-Flop (FF) with stacked transistors based on the Adaptive Coupling Flip-Flop (ACFF) with low power consumption in a 65 nm FDSOI process. The slave latch in ACFF is much weaker against soft errors than the master latch. We design several FFs with stacked transistors in the master or slave latches to mitigate soft errors. We investigate radiation hardness of the proposed FFs by α particle and neutron irradiation tests. The proposed FFs have higher radiation hardness than a conventional DFF and ACFF. Neutron irradiation and α particle tests revealed no error in the proposed AC Slave-Stacked FF (AC_SS FF) which has stacked transistors only in the slave latch. We also investigate radiation hardness of the proposed FFs by heavy ion irradiation. The proposed FFs maintain higher radiation hardness up to 40 MeV-cm2/mg than the conventional DFF. Stacked inverters become more sensitive to soft errors by increasing tilt angles. AC_SS FF achieves higher radiation hardness than ACFF with the performance equivalent to that of ACFF.

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© 2018 The Institute of Electronics, Information and Communication Engineers
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