IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Fundamentals and Applications of Advanced Semiconductor Devices
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
Jang Gn YUNIl Han PARKSeongjae CHOJung Hoon LEEDoo-Hyun KIMGil Sung LEEYoon KIMJong Duk LEEByung-Gook PARK
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2008 Volume E91.C Issue 5 Pages 742-746


In this paper, characteristics of the 2-bit recessed channel memory with lifted-charge trapping nodes are investigated. The length between the charge trapping nodes through channel, which is defined as the effective memory node length (Meff), is extended by lifting up them. The dependence of VTH window and short channel effect (SCE) on the recessed depth is analyzed. Improvement of short channel effect is achieved because the recessed channel structure increases the effective channel length (Leff). Moreover, this device shows highly scalable memory characteristics without suffering from the bottom-side effect (BSE).

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© 2008 The Institute of Electronics, Information and Communication Engineers
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