An Energy Efficient 2-Read/Write 8T Dual-Port SRAM with Disturbance Aware Self-Adjustable Replica Tracking Circuit

抄録

An energy-efficient 2-read/write (2RW) dual-port (DP) SRAM with a new disturbance aware replica scheme has been demonstrated. This scheme aims to generate internal critical timing signals for sense-enable (SE) triggers and wordline (WL) negating paths during the readout operation. By placing individual replica circuits for each port, appropriate internal delays are generated self-adjustably, whether accessing same-row or different-row. Even when the two clock inputs have different phases and frequencies, the proposed replica circuit effectively generates internal timings by mimicking the discharge speeds of each bitline (BL) using replica 8T DP bitcells. A prototype of a 256-kbit DP SRAM macro has been implemented in 90 nm logic CMOS technology. Measurement results show that the dynamic power consumption in the cell array is reduced by 16.6% compared to the conventional replica scheme at a typical supply voltage of 1.2 V and room temperature.