Establishment of Reliability Model for Circuit-Level Chip Constant Stress Accelerated Degradation Data Based on Wiener Process

Abstract

We propose a method for reliability research at the circuit-level chips. The degradation model used combines the Wiener process and the Arrhenius acceleration model. The degradation data analyzed is the pin leakage current sampled during the constant stress acceleration degradation test of Flash memory chips at different temperatures. This method has low testing costs while providing a comprehensive reflection of the degradation conditions of the tested samples. In this work, we established the model through mathematical derivation, and then estimated the distribution of the model parameters by generating bootstrap samples. Then, under the premise of completing the model accuracy test, we completed the estimation of the remaining life of the sample through Monte Carlo simulation.