IEICE Transactions on Information and Systems
Online ISSN : 1745-1361
Print ISSN : 0916-8532
Special Section on Reconfigurable Systems
A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs
Krzysztof JOZWIKHiroyuki TOMIYAMAShinya HONDAHiroaki TAKADA
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2012 Volume E95.D Issue 2 Pages 345-353

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Abstract

Modern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.

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© 2012 The Institute of Electronics, Information and Communication Engineers
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