Recent Trends in Planarization Polishing Technology for a Semiconductor Substrate Manufacturing

―Development of Polishing Simulation―

Abstract

The surface of a semiconductor substrate is flattened with high accuracy by a planarization polishing technique. To obtain the high flatness for a large sized wafer, various polishing simulations have been developed. The first part of this report describes the polishing simulation theory and some applications for a single side polishing. The simulation used for the oscillation polishing with a small tool calculates the change of the wafer profile and optimizes the oscillation speed distribution to obtain the flatness of 0.1μm. The latter part of this report introduces a simulation for a double side polishing, the idea of calculating the pressure distribution and a simulation example.