1992 年 16 巻 34 号 p. 25-30
This paper describes realtime processing systems of HDTV signals using parallel processors. An HD-VSP system and an HDTV programmable codec are introduced here. For conventional TV signal processing, a basic parallel processors architecture is already established. In addition to the basic architecture, data rate conversion technique is employed to reduce high sampling rate of HDTV signals. Furthermore, on the HDTV programmable codec, accelerators are combined with parallel processors to realize higher performance. Total performance of the HD-VSP system is 2.5 GOPS and that of the HDTV programmable codec is 15 GOPS at maximum.